1. Field of the Invention
The invention relates to a cache subsystem for a computer system and, more particularly, to a cache subsystem configured for operation with a selected one of at least two different sized cache memories.
2. Description of Related Art
As is well known to those skilled in the art, a computer system consists of a number of subsystems interconnected by communication paths or busses that transfer data between the subsystems. A typical computer system includes a central processing unit (or "CPU") which comprises the processor subsystem and a plurality of memory and storage devices (or "memory"). The processor subsystem controls the operation of the computer system by executing a sequence of instructions to perform a series of mathematical operations on data. Both the instructions and the data are stored in the computer's memory as binary information in patterns of logical ones and zeros. To transfer data between the processor subsystem and the memory, typical computer systems are provided with a data bus for carrying data to and from the memory, an address bus for carrying signals used to locate specific memory and subsystem addresses and a control bus for carrying timing and control pulses to all subsystems included in a computer system.
The memory of a computer system may be comprised of a plurality of memory subsystems. The predominant memory subsystem is generally referred to as the main memory and is typically composed of dynamic random access memory (or "DRAM") chips. Data and program instructions brought from disk or tape are stored in main memory for use by the processor subsystem. Many computer systems also include a second memory subsystem generally referred to as the cache memory subsystem. Instead of DRAM chips, cache memory subsystems are made up of static random access memory (or "SRAM") chips, thereby resulting in a memory up to two times faster than the main memory. Most cache memory subsystems are used to store operating instructions as well as data likely to be needed next by the processor subsystem, thereby speeding up the operation of the computer system. Cache memory is up to two times faster than main memory and is designed to hold the operating instructions and data likely to be required most frequently by the CPU, thereby reducing the memory access time of the processor subsystem. Finally, a small amount of memory within the CPU is called CPU memory or registers. Made of SRAM circuits which are optimized for speed, data registers within the processors are the fastest memory of all. A program register stores the location in memory of the next program instruction while an instruction register holds the instruction being executed and a general purpose register briefly stores data during processing.
Based upon the foregoing, it should be appreciated that it is known to those skilled in the art to include a cache memory configuration in a computer system to provide a place for fast local storage of frequently accessed data.
A printed circuit board is a device for supporting electronic components mounted on its surface and for electrically interconnecting them with one another. Advances in integrated circuit technology have made possible the construction of computer subsystems such as a cache memory subsystem on one such printed circuit board. In its most elementary form, a printed circuit board consists of a nonconductive substrate clad with a thin layer of metal from which portions are etched away to form a pattern of electrical conductors. Glass/epoxy fiberglass is a commonly used substrate material and copper is commonly used for the thin layer of metal covering one or both surfaces of the substrate.
The simplest printed circuit boards have only one layer of wiring, often placed on the side of the substrate opposite the mounted components. More complex printed circuit boards also have conductive wiring patterns disposed on both the upper and lower surfaces of the insulative substrate, which allows the interconnection of many more components on a single board. Multilayer printed circuit boards are used in extremely complex circuits and include a plurality of layers of conductive wiring patterns sandwiched between thin insulative substrate layers and interconnected with one another by means of conductive holes extending through one or more of the substrates.
Constructing printed circuit boards, especially those having a plurality of layers of conductors and insulative substrates, is fairly time consuming and involved. The first step in preparing a printed circuit board is to create a photographic transparency of the circuit layout, in which the pattern of the conductors is opaque to light. Next, the transparency is projected onto the board after the layer of conductive material covering the surface of the insulative substrate has been coated with a film of photoresist material that hardens upon exposure to light. Washing away the soft parts of the film in a chemical bath leaves a photoresist pattern on the substrate which is the inverse of the circuit transparency. The conductive pattern which is not protected by the photoresist is coated with solder to protect it and then the copper or other metal that is not covered by the solder plating is etched away. Circuitry on different layers of a multilayer printed circuit board are joined by holes drilled transversely through the different layers which are plated with copper to electrically interconnect the circuits.
Based upon the foregoing, it should be appreciated that printed circuit boards, with their elaborate interconnections, are difficult and costly to build. When manufacturing a cache memory subsystem for a computer system, the system designer would determine the cache memory size required for the particular computer system, design a cache memory subsystem for incorporation into the aforementioned computer system, test the cache memory subsystem for conformance with design specifications and then begin the production of printed circuit boards with the cache memory subsystem manufactured thereon. The cache memory subsystem would then have to be serviced throughout the life of the computer system. As will be more fully described below, the size of the cache memory subsystem controls the amount of information which is quickly accessible to the user. Thus, depending on the particular operating characteristics desired for the computer system, different sized cache memory subsystems are required for different computer systems.
The requirement of different sized cache memory subsystems for different computer systems has been a particularly expensive problem for computer system manufacturers, particularly those manufacturing multiple computer system designs. Unless, the different systems require the same sized cache memory subsystem, the manufacturer must often design, test, manufacture and service any number of multiple cache memory boards. The cache memory subsystem also poses problems for the user as well. In order to upgrade a computer system to one with a larger cache memory, and thereby obtain faster data processing, a user would have to, at worst, replace the entire system and, at best, replace the entire cache memory board. Either alternative is an expensive proposition.
Providing multiple possible electronic circuit configurations on a single printed circuit board, thereby saving the expense of multiple different printed circuit boards for each circuit, has long been sought after as a manufacturing technique. U.S. Pat. No. 4,859,190 to Anderson is directed to a printed circuit board having a pattern of multiple groupings of connector holes which provide for the interconnection of two different types of connectors into the same area of the printed circuit board. The Anderson patent contemplates the use of multiple groupings so that the main printed circuit board may alternately be connected via a first connector to a first subsidiary printed circuit board or via a second connector different from the first connector, to a second subsidiary printed circuit board. Anderson does not address printed circuit boards designed for multiple configurations.
U.S. Pat. No. 4,190,901 to Johnson et al is directed to a printed circuit board which includes a first set of holes for mounting groups of integrated circuit chips required to construct a first memory subsystem and a second set of holes for mounting groups of integrated circuit chips required to construct an alternative memory subsystem. During construction, the printed circuit board is populated with only those integrated circuit chips required for the construction of a memory subsystem with one or more selected features. The Johnson et al patent concentrates on the production of alternate memory subsystems and is not particularly directed toward the construction of a single memory subsystem which, with minor modification, can be reconfigured to serve other needs. U.S. Pat. No. 4,255,852, also to Johnson et al, is related to this same general area.